1. Field of the Invention
The present invention relates to the field of capacitor layout schemes for integrated circuits.
2. Background Art
In analog and mixed signal integrated circuit applications, capacitance ratios are used to precisely determine a specified output quantity or value. Examples of such applications include the chord ratio in a digital-to-analog converter (DAC) as well as the filter frequency for a switched capacitor circuit. Capacitors are typically formed of two polysilicon layers where POLY1 and POLY2 denote the bottom and top layers, respectively. The two polysilicon layers, or plates, sandwich a thin layer (typically 250 .ANG.-500 .ANG.) of thermally grown silicon dioxide, thereby forming a MOS capacitor structure.
Capacitor ratios are used instead of an absolute capacitance value, so that the effects of small variations in photolithography masks and wafer processing are suppressed. In practice, unit capacitors are used as building blocks. A unit capacitor, or unit cell, is a capacitor having a standard, predetermined size and shape, typically a square. All capacitors on an integrated circuit that are to be related to each other by predetermined capacitor ratios are made of groups or arrays of electrically interconnected unit cells. The unit capacitors are connected together to form larger capacitances that are the numerator or denominator of a capacitance ratio. Since the unit capacitors are identical and are processed simultaneously, mask and processing variations should not vary across the relevant portion of a die. In theory, these variations affect each unit capacitor equally and, therefore, have no effect on the capacitance ratios.
The accuracy of capacitance ratios has a significant effect on integrated circuit performance. For example, the chord ratio of an 8-bit DAC requires 0.4% accuracy and a 10-bit chord ratio requires 0.1% accuracy. A high Q notch filter centered at 1786 Hz that has a 0.4% accuracy has a possible error shift of 7 Hz. Such an error shift can significantly affect the attenuation at the design frequency. Circuit designers can efficiently convert 0.1% capacitor ratio accuracy into higher performance; one tenth of a percent (0.1%) of a 20 .mu.m unit capacitor is only 0.02 .mu.m or 200 .ANG..
In practice, however, there are several nonideal characteristics, both known and predicted, that undermine the accuracy of the capacitance ratios.
A disadvantage of the prior art are proximity effects in the photolithography and etching steps that produce variations in individual capacitor sizes. For example, the distance between a unit capacitor and its nearest neighbor has an effect upon the exposure, photoresist development, and etching of a unit capacitor edge. This occurs as result of chemical loading or optical interference. Limited improvement has been made by placing guard-rings around each group of unit capacitors. However, the amount of etched area within an area perimeter of an edge can also affect chemical loading. This area has been shown to extend as far as 50 .mu.m from the edge.
Another disadvantage of the prior art is that the POLY1 capacitor plate is normally common to all of the unit capacitors that form one capacitance. Therefore, depending on the location of a unit capacitor within a group of unit capacitors, the fringe capacitance between the top of the POLY2 unit capacitor plate and the common POLY1 plate varies. Models indicate that the variation can be as much as 0.4% among 27 .mu.m unit capacitors. This problem is worsened by the fact that the fringe capacitance varies according to the dielectric constant of the material many microns above the POLY2 layer. The material above the POLY2 layer is primarily air which has a dielectric constant .epsilon. of .epsilon..sub.o (8.86.times.10.sup.-14 F/cm) at wafer probe and plastic filler (.epsilon.=3.8.epsilon..sub.o) at package test.
A further disadvantage of the prior art is that unit capacitors in a capacitance are connected together with metal interconnect lines, and these lines run over the POLY1 plate between the POLY2 plates. This produces parasitic capacitance that is about 1.3 Fl or about 0.25% of the unit capacitance in a typical 27 .mu.m design. Therefore, the number of interconnects per unit capacitor must be kept constant to prevent any mismatch. This is complicated by the fact that some of the interconnects are between unit capacitors in a group and others connect the group to external circuitry. These latter interconnects cross the edge of the POLY1 plate where the exposed POLY1 length is different than the length between unit capacitors. The exposed POLY1 length at the edge is subject to misalignment between the POLY1 and POLY2 layers; also, there is additional fringe capacitance at the edge. Thus, the interconnects are usually not apportioned exactly into ratios.
Yet another disadvantage of the prior art is that there must be two interconnects from unit capacitor groups (called capacitances here) to external circuitry where one is for the series of POLY2 upper plates and one is for the POLY1 lower plate. When these two interconnects run close to each other or the upper plate POLY2 interconnect runs next to the lower plate POLY1, significant parasitic capacitance results.
Another disadvantage of the prior art is that, in order for the capacitance ratio to remain constant despite small but uniform variations in unit capacitor line-width, the capacitance perimeter ratio must be the same as the capacitance area ratio. In this way, a small overetch or underetch produces the same proportional change in the numerator and denominator capacitance. If the desired ratio is an integer as in a DAC, the use of unit capacitors accomplishes this automatically. However, in a filter, the ratio is typically a non-integral number, and one non-unit capacitor must be used to produce the proper perimeter ratio.